Trench isolation structure, semiconductor assembly comprising such a trench isolation, and method for forming such a trench isolation

ABSTRACT

The present invention provides a trench isolation structure, comprising a trench groove ( 4 ) in a semiconductor slab ( 1 ) with a buried layer ( 2 ). The trench groove ( 4 ) is lined with first insulating material ( 5 ), then filled with a first filler material ( 6 ) up to the level of the buried layer. Then second insulating material ( 7 ), for example an oxide, is preferably applied in the volume which is surrounded by the buried layer ( 2 ). The remaining part of the trench groove ( 4 ) is either filled with second filler material ( 8 ) or with second insulating material. Said structure provides lower capacitive coupling between buried layer ( 2 ) edge and substrate ( 1 ), with improved thermal behavior. The invention furthermore provides a semiconductor assembly comprising said trench isolation structure and at least one semiconductor device, as well as a method for forming such a trench isolation structure.

The present invention relates to a trench isolation structure,comprising a slab of semiconducting material having a surface and aburied layer which extends parallel to the surface, and a trench groovewhich extends at least from the surface through the buried layer down toa part of the slab below the buried layer and which comprises a firstinsulating material having a thickness on a wall of the trench groove,and wherein a remaining part of the trench groove is at least partiallyfilled with a first filler material.

Furthermore, the invention relates to a semiconductor assembly,comprising such a trench isolation structure, and at least onesemiconductor device present on the surface of the slab ofsemiconducting material, wherein the semiconductor device is insulatedby means of the trench isolation structure.

The present invention also relates to a method for forming a trenchisolation in a semiconductor slab, comprising the steps of:

-   providing a slab of semiconducting material having a surface and    comprising a buried layer parallel to and below the surface; forming    a trench groove in the semiconductor slab, the trench groove having    a bottom surface and a sidewall, and extending from the first    surface through the buried layer and into the slab of semiconducting    material; filling the trench groove at least with a first insulating    material and with a first filler material, wherein the first    insulating material covers at least the bottom surface and the    sidewall in a layer having a thickness d, and wherein the first    filler material at least partially fills a remaining part of the    trench groove.

Generally, in high-performance bipolar and BiCMOS processes, deep trenchisolation is applied in order to reduce parasitic capacitances, improvepacking densities and improve device isolation. With decreasing devicedimensions, an increasing part of the collector-substrate capacitancefor minimum size transistors is contributed by the edge of the buriedlayer-substrate junction (perimeter contribution). With the use of adeep trench isolation which reaches through the buried layer, thiscontribution can be reduced significantly. Furthermore,collector-collector spacing can be reduced without violating breakdowndemands. Ordinarily, in order to minimize collector-substratecapacitance, a material with low dielectric constant (e.g. silicondioxide) would be preferable to fill up the trenches completely.However, a complete BiCMOS-process can introduce thermally inducedstress, due to mismatch of the thermal expansion coefficients of thedielectric material and the silicon substrate. It can also influenceelectrical characteristics. Therefore, a polysilicon filled deep trenchwith a thin dielectric liner is generally applied.

U.S. Pat. No. 5,966,598 discloses a trench isolation structure and amethod for forming such a trench isolation structure. The trenchisolation structure comprises an epitaxial layer, a buried layer, asilicon substrate. Trench grooves extend vertically through theepitaxial layer and the buried layer. In one embodiment, a lower part ofthe trench groove, which part extends from the substrate all through theburied layer to the epitaxial layer, is filled with polysilicon, while aremaining part is filled with an insulator. In another embodiment, asilicon oxide film is present below the buried layer. The bottom surfaceof trench groove extends through the buried layer and reaches aninterface between the silicon oxide layer and the buried layer. A firstinter-layer insulator is formed on both vertical side walls and a bottomwall of each trench groove. Polysilicon films are provided which fill uplower regions of the trench grooves. A second inter-layer insulator isprovided on the polysilicon films within the trench grooves so that thesecond inter-layer insulator fills up the upper region of the trenchgroove.

A problem with the known trench isolation structures is that they do notprovide at the same time low parasitic capacitance values and minimumstress generated due to mismatch of thermal expansion coefficients. Thislimits the integration in a full BiCMOS process. It specifically limitsthe reduction of collector-collector spacing or minimum devicedimensions in general.

It is an object of the present invention to provide an improved trenchisolation structure of the indicated kind, which provides favourableparasitic capacitance values while ensuring at the same time goodinsulating properties and low thermally induced stress, when used in asemiconductor device assembly. In this way, a smaller minimum deviceassembly dimension becomes possible.

Said object is achieved by a trench isolation structure according to theinvention, which is characterized in that at least in a first part ofthe trench groove which is surrounded by the buried layer, the thicknessis larger than the thickness in a second part of the trench groove whichis located below the first part.

The present inventor has found that with such a trench isolation, i.e.having a layer of first insulating material with a thickness at thelevel of the buried layer which is larger than the correspondingthickness below the buried layer, offers a sufficiently low parasiticcapacitance, while the stress generated due to the mismatch of thethermal expansion coefficients is minimized. Furthermore, a separateinsulating layer in the slab, such as the silicon dioxide layer in thecase of the cited US patent, is no longer necessary. Hence a simplerconstruction with improved characteristics may be obtained.

Here, the words “surrounded by” indicate that the first part is locatedwithin a volume of the trench groove bounded by the sidewalls of thetrench groove and by an upper surface and a lower surface which are atthe same level or depth as an upper surface and a lower surface,respectively, of the buried layer. It is not necessary, thoughpreferable, that the first part completely occupies the volume asdescribed above.

Within the framework of the present invention, such words as “below”,“above”, “lower”, “upper”, and so on, are to be considered with respectto the semiconductor slab, as seen in a direction perpendicular to thesurface thereof E.g. “below” means “at a greater depth below the surfaceof the semiconductor slab”.

Generally, the semiconductor slab is a substrate, onto which the buriedlayer is deposited, or formed in any other fashion. On top of the buriedlayer, another layer of semiconducting material is formed. In mostcases, this will be an epitaxial layer of semiconducting material. Forthis application, the assembly of the slab semiconducting material, theburied layer and the other (e.g. epitaxial) layer of semiconductingmaterial is sometimes called the slab. It will be clear in which casesonly the substrate, or lowest part of this assembly is meant.

The thickness of the first insulating material is a function of positionin the trench groove, in particular of the depth below the surface ofthe slab. According to the invention, this thickness in the part of thetrench groove located below the first part is smaller than the thicknessin the first part.

Preferably, the thickness in the first part is larger than the thicknessin a third part of the trench groove which is located above the firstpart. In this way it is ensured that the resulting region with firstinsulating material is as small as possible without giving up theadvantages according to the present invention. In other words, the firstinsulating material is present only at the location where its effectsare largest, in particular at the level of the buried layer. Since thisburied layer can carry a relatively large part of (induced) currents,the insulating and capacitance properties at this level shouldpreferably be optimum. However, it is possible that the thickness in thethird part is larger than the thickness in the first part, e.g. if thetrench groove has diverging sidewalls, the width being largest near thesurface of the slab, and the first and third part of the trench grooveare completely filled with the first filler material. In the case of atrench groove with parallel sidewalls, this effect is not likely tooccur.

Advantageously, the first part is completely filled with the firstinsulating material. This means that only first insulating material ispresent in a cross-section taken through the first part of the trenchgroove, in a plane parallel with the plane of the buried layer. Theadvantageous properties, in particular the insulating properties, of afirst part of such design are optimum. However, it is possible to use afirst part which is partly filled with another suitable material, forexample a first filler material. In such a first part, the firstinsulating material may come in a layer with an increased thickness whencompared to the thickness in other parts of the trench groove.

In a preferred embodiment, the first part extends substantially in linewith the buried layer. This means that the first part has an uppersurface and a lower surface, which when extended coincide with the uppersurface and the lower surface of the buried layer, respectively. Theterm “substantially” indicates that the distance between the associatedlower surfaces and upper surfaces, respectively, may be up to 10% of thethickness of the buried layer, e.g. to account for unevenness in saidsurfaces. This way, the volume taken up by the first part is bounded bythe layer of first insulating material on the sidewalls of the trenchgroove, and by the lower and upper surfaces of the second insulatingmaterial. For practical purposes, the first part may be thought ofextending also to that part of the layer of first insulating materialbetween the sidewalls and the volume of second insulating material.

A preferred first insulating material comprises an oxide material, morepreferably silicon oxide. Silicon dioxide is a very good insulator witha favourably low dielectric constant. It also has the advantage that itis very easy to provide the trench groove with silicon dioxide. This maybe done e.g. by means of deposition via tetra ethyl ortho-silicate(TEOS), or high density plasma deposition (HDP). Other methods likeoxidizing the silicon of the slab are not excluded, however.

An advantageous first filler material comprises silicon, preferablypolysilicon. This material is very suitable to ensure favourable thermalbehaviour, since it differs little or not from the material of thesemiconductor slab itself. Of course, if the semiconductor slabcomprises a different material, e.g. germanium, or gallium arsenide, thefirst filler material could be selected accordingly, preferably thecorresponding semiconducting material.

The invention provides an advantageous semiconductor assembly,comprising a trench isolation structure according to the invention, andat least one semiconductor device present on the surface of the slab ofsemiconducting material, wherein the semiconductor device is insulatedby means of the trench isolation structure.

Such a semiconductor assembly may offer faster switching speed and/orimproved thermal behavior at smaller dimensions. Furthermore, such anassembly may be fabricated with a smaller distance between thesemiconductor devices, in the case of multi-device assemblies. This isallowed by the trench isolation structure according to the invention,which offers an improved combination of insulating and thermal stressproperties at the same inter-device distance, or equal such propertiesat a reduced inter-device distance, when compared to conventional trenchisolation structures.

Although the semiconductor device in an assembly according to theinvention is not particularly limited, the semiconductor devicespreferably comprise transistors, and more preferably bipolar or bipolartransistors in a BiCMOS process. The demands with respect to suchcomponents are very high, and improvements in respect of theirapplication are very important throughout the semiconductor andelectronics industry.

The method by which a trench isolation structure according to theinvention is obtained is not critical, as long as it results in theadvantageous described trench isolation structure. However, theinvention provides a preferred method of the kind mentioned in theintroduction, characterized in that at least in a first part of thetrench groove which is surrounded by the buried layer, the thickness ismade larger than the thickness in a second part of the trench groovewhich is located below the first part.

As mentioned hereinbefore, by selecting the thickness as indicated, thefavourable combination of good capacitance properties and reducedthermal stress can be obtained.

In an advantageous method, the thickness in the first part of the trenchgroove is made larger than the thickness in a third part of the trenchgroove which is located above the first part. The same advantages asdescribed in respect of a preferred trench isolation structure hold forthis method.

The step of filling the trench groove in a way proposed by the presentinvention is not particularly limited. Any method known in the art toprovide the layer of first insulating material with the indicatedthickness d, as well as the filling with the first filler material maybe used. Preferably however, the step of filling the trench groovecomprises the steps of covering the bottom surface and the sidewalls ofthe trench groove with a layer of first insulating material; filling thetrench groove with a first filler material at least to a lower surfacelevel of the buried layer; removing the first filler material down to alevel which is substantially flush with the lower surface level of theburied layer; and filling the remaining part of the trench groove atleast partially with a second insulating material.

This offers a very simple method of forming a trench isolation accordingto the invention, with a minimum number of steps, and hence withincreased reliability.

As the first insulating material in principle any material known in thestate of the art may be selected. However, preferably silicon dioxide isselected. Said silicon dioxide may for example be deposited by means oftetra ethyl ortho-silicate (TEOS). Any other insulating material may beused as well however. Preferably, the second insulating materialcomprises the same material as the first insulating material. However,said insulating materials may be obtained by means of differentprocesses, or may be different materials altogether. The thickness ofthe layer can have any desired value, as long as the insulatingproperties are satisfactory. Preferably, the minimum thickness is atleast 100 nm.

The next step is the filling of the trench with the first fillermaterial at least to a lower surface level of the buried layer. Thelower surface level of the buried layer is meant to indicate thatsurface of the buried layer which lies deepest in the slab ofsemiconducting material. Said step of filling the trench with the firstfiller material may be performed according to any known method. Saidfilling step comprises filling the remaining part of the trench at leastto the lower surface level of the buried layer, and more preferablycompletely filling the remaining part of the trench groove, with thefirst filler material. It further comprises the step of removing thefirst filler material down to a level which is substantially flush withthe lower level of the buried layer. In this way, a very good controlover the properties of the first filler material can be obtained.

The next step is filling the remaining part at least partially with asecond insulating material. As mentioned before, the second insulatingmaterial may be the same material as the first insulating material, ormay be substantially be the same material but obtained through adifferent method, or may be different from the first insulatingmaterial. Examples are silicon dioxide obtainable by means of depositionfrom TEOS, or by HDP.

Advantageously, the step of filling the remaining part with the firstfiller material is followed by the steps of removing the secondinsulating material down to a level which is substantially flush with anupper surface level of the buried layer, and filling the remaining partof the trench groove with a second filler material.

The second filler material may be the same as the first filler material.However, in many cases it will be preferably to then cover said secondfiller material with a protective layer, e.g. another insulatingmaterial such as an oxide. Hence it may be preferred to use a differentsecond filler material, which need not be covered with yet anothermaterial. However, care should be taken not to affect the thermal and/orelectrical properties of the trench isolation structure.

In a preferred embodiment, the step of removing the first fillermaterial and/or of the second insulating material comprises etching thematerial. Although the step of removing the first filler material may beperformed by any known method, etching by means of any appropriateetchant is preferred, because of the good control over the properties ofthe materials left behind, in particular the surface quality and purity.

The invention will now be explained in more detail, with reference tothe accompanying drawings, in which:

FIG. 1 shows in cross-section a first embodiment of the trench isolationstructure according to the invention;

FIG. 2 shows in cross-section a second embodiment of the trenchisolation structure according to the invention;

FIGS. 3 a-g show a block diagram of the first embodiment of the methodaccording to the invention, resulting in the trench isolation structureof FIG. 1;

FIGS. 4 a-e show a block diagram of the second embodiment of the methodaccording to the invention, resulting in the trench isolation structureof FIG. 2; and

FIG. 5 shows a diagrammatic cross-section of a semiconductor deviceisolated by means of trench isolation structures according to theinvention.

FIG. 6 shows a diagrammatic third embodiment of the trench isolationstructure according to the invention.

In FIG. 1, 1 indicates a semiconductor slab, 2 denotes a buried layer,having an upper surface 2 a and a lower surface 2 b, and 3 denotes anepitaxial layer.

A trench groove is indicated by 4. The trench groove 4 comprises a liner5 of a first insulating material, a first filler material 6, a secondinsulating material 7, having an upper surface 7 a and a lower surface 7b and a second filler material 8.

A shallow trench is indicated by reference numeral 9.

The semiconductor slab 1 is made of silicon, or another suitablesemiconducting material, and serves as a substrate for e.g.semiconductor devices. Here, the slab of semiconducting material is alightly doped p material (p−), although n materials are not excluded. Asshown in FIG. 1, the trench structure, according to an embodiment of thepresent invention, is depicted in three parts, a 1^(st) part, 2^(nd)part, and a 3^(rd) part, so as to aid in the discussion herein.

The buried layer 2 consists of a layer of heavily doped material havingopposite polarity, here (n+). Generally, it has a layer shape withsubstantially flat and parallel upper and lower surfaces 2 a and 2 b,respectively. The buried layer may be fabricated by any known method,e.g. deposition techniques, ion implanting etc.

On top of the buried layer an epitaxial layer 3 is deposited, againthrough any known technique. Here the epitaxial layer 3 consists oflightly doped semiconductor material having a negative polarity, hencen− material.

It should be noted that, for the purposes of this invention, theassembly of semiconductor slab 1, buried layer 2 and epitaxial layer 3is sometimes also called the semiconductor slab. The context willindicate clearly the cases whether the assembly is meant, or whetherspecifically the semiconductor slab, or substrate, is meant.

The dimensions of the features may be described in reference to FIG. 1,a cross-section of the structure according to an embodiment of thepresent invention. For the purposes of discussion, a “thickness” of afeature is measured in a horizontal direction parallel to the surface ofthe semiconductor slab, as denoted in the FIG. 1. A “depth” of a featurewould be a measured in a direction perpendicular to the surface of thesemiconductor slab, also denoted in FIG. 1. The “length” of a feature ismeasured in a direction perpendicular to the cross-section, denoted inFIG. 1.

A trench groove 4 is formed in the assembly of epitaxial layer 3, buriedlayer 2 and semiconductor slab 1. The trench groove 4 should be deepenough to go through the buried layer 2, and extend into thesemiconductor slab 1, in order to optimally insulate the one or moreparts to be insulated. This is called a deep trench isolation.

The shape of the trench groove 4 may vary according to requirements.However, it will mostly be in the form of a trench groove of somelength, extending substantially perpendicularly with respect to thesurface of the semiconductor slab 1, 2, 3. In some cases, though, it maybe advantageous to form trench grooves which extend non-perpendicularly,e.g. slanting, with respect to the surface of the semiconductor slab.

The sidewalls of the groove may be substantially parallel, as may beobtained by e.g. certain etching techniques, or they may be slightlytapering towards a bottom surface of the trench groove. The latter meansa slightly larger maximum width of the trench groove 4, but allows abetter control over the filling of the trench groove.

The trench groove 4 is covered with a layer or liner of a firstinsulating material 5 on its sidewalls and bottom surface, i.e.completely. Here the first insulating material is silicon oxide,deposited by means of TEOS, to a layer thickness of e.g. 125 nm. In mostcases, the first insulating material will be produced by oxidizing thematerial of the sidewall. Besides TEOS, other methods may be used, suchas HDP (high density plasma oxides), and HTO (high temperature oxides).Moreover, it is also possible to deposit an altogether differentmaterial, of course having desirable insulating and dielectricproperties (low ∈). Many such materials are known to the person skilledin the art. The layer thickness indicated here, and throughout the restof this application, depends on the insulating material used. Morespecifically, the lower the ∈ of the material, the thinner the layer maybe. For the oxides discussed here, it turned out that a layer thicknessof 100 nm or more is desirable to obtain a sufficiently low capacitivecoupling.

In a lower part or bottom part of the trench groove 4 up to the lowersurface 7 b of second insulating material, to be described below, afirst filler material 6 is present, in this case polycrystalline silicon(polysilicon) deposited by means of LPCVD (low pressure chemical vapourdeposition) or other processes. Minimum thermal expansion coefficientmismatch with the surrounding semiconductor material is guaranteed.

In FIG. 1, a second insulating material 7 is present and occupies avolume which is in line with the buried layer. The volume has a lowersurface 7 b and an upper surface 7 a, tangent planes through whichsubstantially coincide with lower surface 2 b and lower surface 2 a ofthe buried layer, respectively. In practice, surfaces 2 a and 7 a on theone hand, and/or surfaces 2 b and 7 b on the other hand, may be presentat depths which differ from each other slightly, say max. 10% of thethickness of the buried layer. Experiments and measurements have shownthat with this configuration, very good electrical properties can beobtained, while the possibly inducable thermal stress is kept to anacceptable minimum. Specifically, the capacitance values at theperimeter (or “edge”) of the buried layer, where it is penetrated by thetrench groove, are good, i.e. low. Said capacitance value is notablylower than in the case of a completely polysilicon filled trench groove.

In a first approximation, the capacitive coupling between the buriedlayer and the substrate (semiconductor material) in a homogeneouslyfilled trench isolation structure is determined by a series connectionof three capacitances. These are the capacitance of the oxide liner, thecapacitance of the filling of the trench, and the capacitance of theoxide liner (i.e. of the opposite wall of the trench). Assuming that ineach case the capacitance is set equal to the dielectric constantdivided by the thickness of the layer (∈_(ox), t_(ox,1) or t_(ox,2) forthe first and second oxide liner, and ∈_(diel) and t_(diel) for thefiller material), then the total capacitance C_(tot) can be shown toequalC _(tot)=∈/(t _(ox,1)+(∈_(ox)/∈_(diel))t _(diel) +t _(ox,2))  (1)In the case of silicon dioxide as the oxide liner, i.e. the firstinsulating material, ∈=3.9. When the trench is filled with polysilicon,we have ∈=11.9, hence a large capacitive coupling. On the other hand,when silicon dioxide is the filler material, we have ∈=3.9, and a muchsmaller capacitive coupling. Hence, filling all of the trench groovewith low ∈ dielectric material gives the best capacitive values, albeitat the cost of a worse thermal behavior, as discussed previously.

It can be shown that the calculation of the capacitive coupling stillholds for a trench groove which is only partly filled with oxidematerial, provided this oxide material is present at the level of theburied layer. Hence it is preferable to apply the oxide material only atthe level of the buried layer. Of course there should still be a lineron the sidewall of the trench groove, of oxide or another suitableinsulating material.

FIG. 2 shows a second preferred embodiment, which is somewhat easier tofabricate. It is to be noted that, in this and the following Figures,like reference numerals refer to corresponding parts. For brevity, thoseparts will not always be elucidated.

In this embodiment, the “slab” comprises a semiconductor slab 1, aburied layer 2, and an epitaxial layer 3. A trench groove 4 is linedwith a first insulating material 5, and a lower part of the trenchgroove 4, up to a lower surface 2 b of the buried layer, is filled witha first filler material 6. The rest of the trench groove 4, in this casebut not necessarily including shallow trench 9, is filled with a secondinsulating material 7.

In certain cases, e.g. semiconductor assemblies with lower thermaldemands, this simpler configuration shows sufficiently improvedcapacitive coupling values, without the difference in thermal expansioncoefficients being too much of a burden.

FIG. 3 a-g show a block diagram of a first embodiment of the methodaccording to the invention, resulting in the trench isolation structureof FIG. 1.

FIG. 3 a shows a slab comprising a semiconductor slab 1, a buried layer2 and an epitaxial layer 3. In the slab a trench groove 4 has beenformed, e.g. by etching.

In a next step, shown in FIG. 3 b, the side- and bottom walls of thetrench groove 4 are covered with an oxide liner 5, through a TEOSprocess or similar. It is to be noted that this detail of the oxideliner is omitted in the FIGS. 3 c-g for clarity reasons.

FIG. 3 c shows a step of filling (by depositing etc.) the trench groove4 with polysilicon as a first filler material 6. Although FIG. 3 cindicates that the trench groove is filled completely, it is to beunderstood that it is only necessary to fill the trench groove at leastup to the lower surface level 2 b of the buried layer 2.

As a next step, shown in FIG. 3 d, any polysilicon above the lowersurface level 2 b of the buried layer 2 is removed, e.g. by etching backthe polysilicon.

FIG. 3 e shows the next step of depositing second insulating material 7,here silicon dioxide, up to the level of the upper surface of the buriedlayer 2. It is to be noted that, strictly speaking, there will be somedeposition of material on top of the layer of first insulating material.However, especially in the case of V-shaped trench grooves, a sufficientopening will remain, in which filler material may be deposited. Ifnecessary, i.e. if the width of the trench would have become too small,a short high frequency “dip” or the like may be used to etch open theupper part of the trench groove.

As a next step shown in FIG. 3 f, a remaining part of the trench groove4 is filled with second filler material 8, here polysilicon. In thiscase, the first 6 and second filler material 8 are the same.

As a final step, shown in FIG. 3 g, oxide material 10 is deposited inorder to fill the shallow trench 9.

The result of the steps of the method shown in FIG. 3 a-g is a trenchisolation structure according to the invention, which is furthermoreprotected at its surface by means of an oxide layer.

FIG. 4 a-e show a block diagram of a second embodiment of the methodaccording to the invention, resulting in the trench isolation structureof FIG. 2.

Steps and FIGS. 4 a-d correspond to steps and FIGS. 3 a-d, and will notbe explained in more detail, for the sake of brevity.

FIG. 4 e shows a final step, in which all of the remaining part of thetrench groove 4 and the shallow trench 9 as well are filled with secondinsulating material 7. Since the second insulating material 7 has twofunctions to fulfill, it may be advantageous to select a somewhatdifferent material. However, in many cases silicon dioxide will be agood choice.

FIG. 5 shows a diagrammatic cross-section of a semiconductor deviceisolated by means of trench isolation structures according to theinvention.

Again, like reference numerals indicate like parts, which holds fornumerals 1 through 10. Furthermore, a semiconductor device isschematically indicated by emitter 11, base 12 and collector 13, while14 indicates a channel stopper known in the art, to improve theproperties of the trench isolation structure. The parts 11-14 may befabricated by any method known in the art. Furthermore it is to be notedthat the parts to be insulated are not limited to such mentioned partsas transistor components base, collector and emitter. Yet in many casesthey will actually be transistors, particularly bipolar or BiCMOStransistors.

The semiconductor device 11, 12, 13 is effectively insulated by means ofthe left and right trench isolation structures. Note that these may betwo cross-sections of a single trench groove encircling thesemiconductor device.

By means of the trench isolation structure the parasitic capacitivecoupling between (in this case) collector and substrate is reducedsignificantly, which means that switching speeds may be increased.Furthermore, since the assembly of semiconductor device insulated bymeans of the inventive trench isolation structure is more resistant tothermally induced stress, a further decrease of inter-device distancemay be obtained. This may further increase the switching speed of thedevice. Of course, these advantages are more explicit in integrateddevices, in which large numbers of devices are close together, than insingle transistor devices.

FIG. 6 shows a diagrammatic third embodiment of the trench isolationstructure according to the invention. Here, the first part comprises anon-continuous layer (as seen in cross-section) of first insulatingmaterial 5.

Actually, the thickness of the oxide liner on the sidewalls is increasedlocally in part A as compared to the thickness thereof on the rest ofthe sidewall. Such local increase in oxide liner thickness may beobtained in a number of ways. E.g. it is possible to start with a trenchgroove, the sidewalls of which have been lined with the first insulatingmaterial (oxide liner) up to a certain thickness, say 100-150 nm. Next,the trench groove is filled with a first filler material up to a lowersurface level 2 b. Next, the thickness of the oxide liner is increasedby depositing more first insulating material on the already existingoxide liner.

A following step would be to anisotropically etch back the firstinsulating material from the top of the first filler material in thetrench groove, followed by filling the groove with first filler materialup to the upper surface level 2 a. As a next step, the oxide liner inthe part of the sidewalls above the upper surface level is selectivelyetched back e.g. to the original thickness, i.e. the layer thickness inthe lower part of the trench groove.

In a final step the remaining part of the trench groove can be filledwith first filler material. In some cases, the trench isolationstructure thus obtained can provide even better control over thecapacitance values, and even less problems due to thermally inducedstress.

Here the first insulating material 5 has an increased thickness in firstpart A, located between upper surface level 2 a and lower surface level2 b. The rest of the trench groove 4 is filled with first fillermaterial 6.

Other ways and methods to obtain the configuration as described aboveare possible and known in the state of the art, although it will beunderstood that generally these are much more complicated than themethods described in connection with FIGS. 1-5. In particular, themethods and construction as shown in connection with FIG. 6 may beuseful for structures in which the semiconductor material comprises Si.Yet the described and other advantages can be obtained in aconfiguration in which the trench isolation structure having anincreased insulating material layer thickness at the level of the buriedlayer.

1. A semiconductor structure, comprising: a slab of semiconductingmaterial having a surface and a buried layer which extends parallel tothe surface, the buried layer having an upper surface and a lowersurface; and a trench groove extending at least from the surface throughthe buried layer down to a part of the slab below the buried layer andthe trench groove including a liner of a first insulating material on awall of the trench groove, and wherein a remaining part of the trenchgroove is at least partially filled with a first filler materialconfigured to provide trench isolation, and wherein the liner ischaracterized by an abrupt increase in thickness in at least a firstpart of the trench groove that is substantially in line with the buriedlayer, the abrupt increase in thickness defining a thickness that islarger than a thickness of the liner in a second part of the trenchgroove, the second part of the trench groove located below the firstpart.
 2. A semiconductor structure according to claim 1, characterizedin that the thickness of the liner in the first part of the trenchgroove is larger than a thickness of the liner in a third part of thetrench groove, the third part of the trench groove located above thefirst part of the trench groove.
 3. A semiconductor structure accordingto claim 1, characterized in that the trench groove is completely linedwith the first insulating material.
 4. A semiconductor structureaccording to claim 3, characterized in that the first part of the trenchgroove extends substantially in line with the buried layer.
 5. Asemiconductor structure according to claim 1, wherein at least onesemiconductor device is at least partially present on the surface of theslab of semiconducting material, and wherein the semiconductor device isinsulated by the trench isolation structure.
 6. A semiconductorstructure comprising: a slab of semiconducting material having a surfaceand a buried layer which extends parallel to the surface; a trenchgroove extending at least from the surface through the buried layer downto a part of the slab below the buried layer, the trench groove having awall that is at least predominately lined and covered by a firstinsulating material from above an upper surface of the buried layer tobelow a lower surface of the buried layer, and the first insulatingmaterial for providing trench isolation and having a common thicknessabove and below the buried layer and having an increased thickness in atleast part of the trench groove that is substantially in line with theburied layer; and a first filler material at least partially filling aremaining part of the trench groove in areas above and below the buriedlayer.
 7. A semiconductor structure according to claim 6, characterizedin that the increased thickness is defined by abrupt transitionsrespectively located near the upper surface of the buried layer and nearthe lower surface of the buried layer.
 8. A semiconductor structureaccording to claim 6, characterized in that the increased thickness issubstantially in line with the buried layer.
 9. A semiconductorstructure according to claim 6, characterized in that the part of thetrench groove extends substantially in line with the buried layer.